What is new in USB4 from a HW designer's perspective?
I know that there are still many blissfully ignorant years ahead of us, nevertheless I took a glimpse of the recently released USB4 specification and would like to share my thoughts here from a hardware-development perspective.
USB4 is coming, and it is not cheap and simple anymore. It is very fast and resembles a computer network now. I suppose it will be horrible to debug.
So, many webpages like Tom's HW or Techcrunch have read the recently released USB4 specification and have been reporting on it, of course mostly from a consumer's point of view.
I know that there are still many blissfully ignorant years ahead of us, I could not resist but took a glimpse of the specification and would like to share my thoughts here from a hardware-development perspective. I will extend this post as I scroll through the document, please consider this as a sketchbook.
Some highlights I have found to be interesting
- We are sticking to the nice and symmetrical USB-C receptacle. I cherish that.
- The high speed differential lanes of the USB4 standard, dubbed Gen3 will have a fastest transfer rate of 20 Gbps, per lane. USB4 has two of those lanes to have a 40 Gbps theoretical limit.
- There is a talk on re-timers, which are buffers that can reinstate the signal integrity needed for the application. There are already similar chips that use the techniques mentioned in the specification for 10Gig ethernet applications. The main idea is to complement the line's RF-lossy transfer function, with a RF boosting gain path. Some serious control theory there.
- Evidently the main goal here is to have one interface to rule them all. In order to achieve that, there will be adapters within the USB4 hosts, hubs and docks that will tunnel PCIe, DisplayPort and USB3 protocols. That means each protocol gets its own protocol adapter in the hardware. This will considerably complicate V&V of the chipsets.
- USB4 hosts, as masters, will be able to setup data exchange between two peripherals. (with minimal intervention, I suppose.) To me, this is a first in the possible topologies of how devices will connect. The connection possibilities are numerous, therefore there was a need for a spanning tree algorithm that will eliminate USB device loops.
- We are looking at stringent insertion losses of 7.5dB at 10GHz, in the whole chain from the connector to the die. To get an idea, here is a whitepaper.
- We have active and passive cables now, which is a new parameter to consider.
- In order to manage all this, USB4 will have an elementary serial channel that operates at 1Mbps, dubbed as the Sideband Channel. It is the USB version of a router management port which host will use to initialize and (an/dis)able lanes, (dis)connect peripherals, and manage power modes.
- I find it elusive that this sideband channel has the bandwidth of a low-speed USB1 connection to operate. Very slack requirements for this lane.
- Following the analogy of a computer network, USB4 routers will need something similiar to an Network Time Protocol (NTP). The routers will support a defined time synchronization protocol.
- USB4 will support Thunderbolt3, and I read that Intel would not incur licensing fees for it to be supported. But, it left up to the vendor implementing USB4, so another parameter to consider there.
- And, yes, all the previous USB standards names are revised.
Meanwhile, there was a buzz yesterday around the spec on Hacker News, go check it out.